This invention relates to the field of computer systems. More particularly, a system and methods are provided for distributing a portion of the processing of received packets among a plurality of threads or processes.
In traditional computing systems, a single process or thread handles the receipt of packets from a hardware module (e.g., a NIC or network interface card). This process, which may be an ISR (Interrupt Service Routine) not only retrieves a packet from a receive descriptor ring and replaces a used buffer, but also makes the received packet available for processing by a higher layer protocol (e.g., IP—Internet Protocol, TCP—Transport Control Protocol), or initiates such processing.
Despite the level of resources in the computer system and the rate of packet arrival, only one packet can be serviced or processed at a time by the ISR. For example, even in a computer system equipped with multiple processors and plenty of memory, generally one processor and thread are called to handle, in serial fashion, every packet received from the hardware module. Many packets may await the attention of the ISR while it is handling a previous packet. The delay encountered by these packets may have a deleterious effect upon the processing efficiency of the computer system.
Therefore, a system and method are needed to decrease the amount of time that an ISR must spend handling each packet that it receives.